1. Field of the Invention
The present invention relates to microprocessors and, in particular, to a data processing system architecture that efficiently integrates a low-cost multiply/accumulate unit.
2. Discussion of the Prior Art
As shown in FIG. 1, a microprogrammed integrated circuit data processing system 10 includes a central processing unit 12 to manipulate data in accordance with operating software that comprises a set of program instructions. Data and program instructions utilized by the CPU 12 are stored in an associated memory 14. Transfer of instructions and data between the CPU 12 and the memory 14 is implemented by a bus interface mechanism which can be part of the CPU 12. Communication between the system 10 and other systems or peripheral devices is accomplished via an input/output device 16.
The memory 14 is typically organized in words, each containing N bits of information, i.e., instructions or data, and each having an address that specifies its location in the memory 14. The CPU 12 retrieves (reads) or provides (writes) information a word at a time by addressing a storage location in the memory 14 and either reading the word stored in that location or writing new information into that location.
Since accessing memory 14 is a slow process relative to the data processing speed of the CPU 12, as shown in FIG. 2, the CPU 12 usually includes an internal register file 18 comprising a number of its own registers which can be read or written very quickly. Since the register file 18 is internal to the CPU 12, many operations can be carried out by the CPU 12 without accessing the memory 14.
As further shown in FIG. 2, the CPU 12 also includes an arithmetic logic unit (ALU) 20 that actually performs the data manipulations specified by the program instructions. The ALU 20 usually receives two operands from the register file 18 via a multiplexor MUX and provides a single result at its output. In some CPU architectures, one of the input operands is always stored in a special internal accumulator register and the result of an ALU operation is always written into this accumulator register.
The CPU 12 also typically includes a shifter 22 for shifting the contents of an internal register, or as shown in FIG. 2, the output of the ALU 20, one or more bits in either direction to provide multiply and divide capability.
Thus, the CPU 12 includes all of the elements necessary to perform all arithmetic and logical data manipulations specified by a program instruction.
To implement a flow of program instructions, that is, to execute the microprocessor's operating program, the CPU 12 relies on a program counter (PC) 24 and its associated control logic to retrieve a series of program instructions and associated data from memory 14. The program counter 24 may simply increment itself through a sequence of program instruction addresses or modify the normal flow of program instructions by responding to special conditions which cause the program counter to "jump" or "branch" to instruction subroutines that depend on the special condition.
In a microprogrammed processor, the actual execution of a particular program instruction is accomplished by performing a specific sequence of microinstructions. Each microinstruction provides the control signals needed to set the ALU 20 to perform a corresponding "micro-operation" and specifies the next microinstruction in the microinstruction sequence for that program instruction.
In some applications, the processor's instruction set includes a program instruction that initiates a microinstruction sequence for performing a series of repetitive math operations to sample or condition data. For example, in so-called digital signal processing (DSP) applications, the processor recovers digital data from a modulated analog input signal utilizing a filtering technique that includes iterative multiply and accumulate steps based on the number of "taps" included in the filter.
A typical DSP multiply-accumulate microinstruction sequence is shown in FIG. 3. First, data is fetched from a sample buffer. Next, filter tap coefficient data is fetched from a coefficient memory. The retrieved data sample (multiplier) and the coefficient (multiplicand) are then multiplied and the resulting product term is added to an accumulating register. The memory pointers are then incremented to repeat the procedure for each filter tap, with product terms being accumulated throughout the procedure to provide a final filter output. The faster the filter throughput, the faster the data can be recovered.
In one prior art approach, the Texas Instruments TI320 DSP Microprocessor, a very fast multiply/accumulate instruction is incorporated into the processor's instruction set. This instruction allows the processor to fetch data, perform the math operations and manage the sample/coefficient memory fast enough to permit practical use of the TI320 processor in DSP applications.
A recognized improvement to the Texas Instruments approach is to add a circular buffer manager unit to the processor. This speeds up the microprocessor by off-loading responsibility for data management.
A circular buffer can be implemented in a number of ways. One popular technique utilizes a set of registers pointing to corresponding locations in memory. One pointer points to the active filter tap sample; this is a dynamic pointer that sequences to the next sample after each multiply operation. A second pointer points to the top of the sample stack. A third pointer points to the bottom of the stack. The circular buffer manager keeps track of the active sample pointer. When the active sample pointer matches the third pointer, it is reloaded to the top of the stack.
It would, however, be desirable to have available a microprocessor that implements a multiply/accumulate function with as few clock cycles as possible for a reasonable hardware cost.